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Semiconductor
April 1999
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DG526, DG527, DG528, DG529
Analog CMOS Latchable Multiplexers
Features
* Direct RESET * TTL and CMOS Compatible Address and Enable Inputs * Maximum Power Supply Rating . . . . . . . . . . . . . . . . 44V * Break-Before-Make Switching * Alternate Source
Description
The DG526, DG527, DG528, and DG529 are CMOS Monolithic 16-Channel/Dual 4-Channel Analog Multiplexers. Each device has on-chip address and control latches to simplify design in microprocessor based applications. The DG526 uses 4 address lines to control its 16 channels; the DG527, DG528 both use 3 address lines to control their 8 channels; and the DG529 uses 2 address lines to control its 4 channels. The enable pin is used to enable the address latches during the WR pulse. It can be hard wired to the logic supply if one of the channels will always be used (except during a reset) or it can be tied to address decoding circuitry for memory mapped operation. The RS pin is used to clear all latches regardless of the state of any other latch or control line. The WR pin is used to transfer the state of the address control lines to their latches, except during a reset or when EN is low. A channel in the ON state conducts signals equally well in both directions. In the OFF state each channel blocks voltages up to the supply rails. The address inputs, WR, RS and the enable input are TTL and CMOS compatible over the full specified operation temperature range.
Applications
* Data Acquisition Systems * Communication Systems * Automatic Test Equipment * Microprocessor Controlled Systemd
Part Number Information
PART NUMBER DG526AK DG526AK/883B DG526BK DG526BY DG526CJ DG526CK DG526CY DG527AK DG527AK/883B DG527BK DG527BY DG527CJ DG527CK DG527CY TEMP. RANGE (oC) -55 to 125 -55 to 125 -25 to 85 -25 to 85 0 to 70 0 to 70 0 to 70 -55 to 125 -55 to 125 -25 to 85 -25 to 85 0 to 70 0 to 70 0 to 70 PACKAGE 28 Ld CERDIP 28 Ld CERDIP 28 Ld CERDIP 28 Ld SOIC 28 Ld PDIP 28 Ld CERDIP 28 Ld SOIC 28 Ld CERDIP 28 Ld CERDIP 28 Ld CERDIP 28 Ld SOIC 28 Ld PDIP 28 Ld CERDIP 28 Ld SOIC PKG. NO. F28.6 F28.6 F28.6 M28.3 E28.6 F28.6 M28.3 F28.6 F28.6 F28.6 M28.3 E28.6 F28.6 M28.3 PART NUMBER DG528AK DG528AK/883B DG528BK DG528BY DG528CJ DG528CK DG528CY DG529AK DG529AK/883B DG529BK DG529BY DG529CJ DG529CK DG529CY TEMP. RANGE (oC) -55 to 125 -55 to 125 -25 to 85 -25 to 85 0 to 70 0 to 70 0 to 70 -55 to 125 -55 to 125 -25 to 85 -25 to 85 0 to 70 0 to 70 0 to 70 PACKAGE 18 Ld CERDIP 18 Ld CERDIP 18 Ld CERDIP 18 Ld SOIC 18 Ld PDIP 18 Ld CERDIP 18 Ld SOIC 18 Ld CERDIP 18 Ld CERDIP 18 Ld CERDIP 18 Ld SOIC 18 Ld PDIP 18 Ld CERDIP 18 Ld SOIC PKG. NO. F18.3 F18.3 F18.3 M18.3 E18.3 F18.3 M18.3 F18.3 F18.3 F18.3 M18.3 E18.3 F18.3 M18.3
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
(c) Harris Corporation 1999
File Number
3139.2
12-1
DG526, DG527, DG528, DG529 Pinouts
DG526 (PDIP, CERDIP, SOIC) TOP VIEW
V+ 1 NC 2 RS 3 S16 4 S15 5 S14 6 S13 7 S12 8 S11 9 S10 10 S9 11 GND 12 WR 13 A3 14 28 D 27 V26 S8 25 S7 24 S6 23 S5 22 S4 21 S3 20 S2 19 S1 18 EN 17 A0 16 A1 15 A2
DG527 (PDIP, CERDIP, SOIC) TOP VIEW
V+ 1 DB 2 RS 3 S8B 4 S7B 5 S6B 6 S5B 7 S4B 8 S3B 9 S2B 10 S1B 11 GND 12 WR 13 NC 14 28 DB 27 V26 S8A 25 S7A 24 S6A 23 S5A 22 S4A 21 S3A 20 S2A 19 S1A 18 EN 17 A0 16 A1 15 A2
DG528 (PDIP, CERDIP, SOIC) TOP VIEW
WR 1 A0 2 EN 3 V- 4 S1 5 S2 6 S3 7 S4 8 D9 18 RS 17 A1 16 A2 15 GND 14 V+ 13 S5 12 S6 11 S7 10 S8
DG529 (PDIP, CERDIP, SOIC) TOP VIEW
WR 1 A0 2 EN 3 V- 4 S1A 5 S2A 6 S3A 7 S4A 8 DA 9 18 RS 17 A1 16 GND 15 V+ 14 S1B 13 S2B 12 S3B 11 S4B 10 DB
12-2
DG526, DG527, DG528, DG529 Functional Diagrams
DG526 16-CHANNEL SINGLE ENDED MULTIPLEXER
V+ VGND
DG527 DIFFERENTIAL 8-CHANNEL MULTIPLEXER
V+ VGND
S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 RS WR DECODER LOGIC AND LATCHES D
S1A S2A S3A S4A S5A S6A S7A S8A S1B S2B S3B S4B S5B S6B S7B S8B RS WR DECODER LOGIC AND LATCHES DB DA
A3
A2
A1
A0
EN
A2
A1
A0
EN
DG528 8-CHANNEL SINGLE ENDED MULTIPLEXER
V+ VGND
DG529 DUAL 4-CHANNEL MULTIPLEXER
V+ VGND
S1 S2 S3 S4 S5 S6 S7 S8 D
S1A S2A S3A S4A S1B S2B S3B S4B DB DA
DECODER LOGIC AND LATCHES LATCHES RS WR WR
DECODER LOGIC AND LATCHES DECODER LOGIC LATCHES RS
A2
A1
A0
EN
A0
A0
EN
12-3
DG526, DG527, DG528, DG529 Schematic Diagrams
LOGIC INTERFACE AND LEVEL SHIFTER
V+ +
LOGIC TRIP POINT REF GND AX , EN, RS, WR
-
TO DECODER
V-
DECODER AND SWITCH
V+ SX
AX` EN` RS` WR` DX V+ DECODER
V-
12-4
DG526, DG527, DG528, DG529
Absolute Maximum Ratings
V+ to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44V V- to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-25V VIN to Ground (Note 1) . . . . . . . . . . . . . . . . . . . . (V- - 2V), (V+ + 2V) VS or VD to V+ (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . +2V, (V- - 2V) VS or VD to V- (Note 1). . . . . . . . . . . . . . . . . . . . . . . . -2V, (V+ + 2V) Current, Any Terminal Except S or D . . . . . . . . . . . . . . . . . . . . 30mA Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA (Pulsed at 1ms, 10% Duty Cycle Max)
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) 18 Ld PDIP Package . . . . . . . . . . . . . . 90 N/A 18 Ld CERDIP Package . . . . . . . . . . . 75 22 18 Ld SOIC Package . . . . . . . . . . . . . . 95 N/A 28 Ld PDIP Package . . . . . . . . . . . . . . 60 N/A 28 Ld CERDIP Package . . . . . . . . . . . 55 18 28 Ld SOIC Package . . . . . . . . . . . . . . 70 N/A Maximum Junction Temperature Ceramic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range C Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65oC to 125oC A and B Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Operating Temperature C Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC B Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC A Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
(Note 3) V+ = +15V, V- = -15V, GND = 0V, WR = 0V, RS = 2.4V, EN = 2.4V, TA = 25oC, Unless Otherwise Specified A SUFFIX B AND C SUFFIX MAX MIN (NOTE 2) TYP MAX UNITS
PARAMETER DYNAMIC Switching Time DG526, of Multiplexer, DG527 tTRANSITION DG528, DG529 Break-BeforeMake Interval, tOPEN DG526, DG527 DG528, DG529 DG526, DG527 DG528, DG529 DG526, DG527 DG528, DG529 DG526, DG527 DG528, DG529 Logic Input Capacitance, CIN DG526, DG527 DG528, DG529 DG526, DG527 DG528, DG529 VS = 0V
(NOTE 6) TEST CONDITIONS
MIN
(NOTE 2) TYP
See Figure 3 (Note 7) See Figure 3 See Figure 4
-
0.65 0.6 0.2 0.2 0.7 1 0.4 0.4 55 68 6 2.5 10 5
1 1 1.5 1.5 1 1 -
-
0.65 0.6 0.2 0.2 0.7 1 0.4 0.4 55 68 6 2.5 10 5
-
s s s s s s s s dB dB pF pF pF pF
Enable and Write Turn-ON Time, tON (EN, WR) Enable and Reset Turn OFF Time, tOFF (EN, RS) Off Isolation, OIRR
See Figures 1, 6 (Note 7) See Figures 5, 6 (Note 7) See Figures 2, 7 (Note 7) See Figures 5, 6 (Note 7) VEN = 0V, R = 1k, CL = 15pF, VS = 7VRMS , f = 500kHz (Note 4)
-
f = 1MHz
VEN = 0V, f = 140kHz -
Source OFF Capacitance, CS(OFF)
12-5
DG526, DG527, DG528, DG529
Electrical Specifications
(Note 3) V+ = +15V, V- = -15V, GND = 0V, WR = 0V, RS = 2.4V, EN = 2.4V, TA = 25oC, Unless Otherwise Specified (Continued) A SUFFIX PARAMETER Drain OFF Capacitance, CD(OFF)T DG526 DG527 DG528 DG529 Charge Injection, Q DG526, DG527 DG528, DG529 INPUT Address Input Current, Input Voltage High, IAH DG526, DG527 DG528, DG529 DG526 DG527 DG528 DG529 VA = 2.4V VA = 15V VA = 2.4V VA = 15V VEN = 2.4V VEN = 0V VEN = 2.4V VEN = 0V All VA = 0V, RS = 0V, WR = 0V -10 -10 -10 -10 -10 -10 0.02 0.02 -0.002 0.006 0.01 0.01 -0.002 -0.002 10 10 -10 -10 -10 -10 -10 -10 0.02 0.02 -0.002 0.006 0.01 0.01 -0.002 -0.002 10 10 A A A A A A A A See Figure 8 VD = 0V (NOTE 6) TEST CONDITIONS VEN = 0V, f = 140kHz MIN (NOTE 2) TYP 65 35 25 12 6 4 MAX B AND C SUFFIX MIN (NOTE 2) TYP 65 35 25 12 6 4 MAX UNITS pF pF pF pF pC pC
Address Input Current, Input Voltage Low, IAL
SWITCH Analog Signal Range, VANALOG Drain Source ON Resistance, rDS(ON) (Note 7) VD = 10V, VAL = 0.8V, VAH = 2.4V, IL = -200A Sequence Each Switch ON -15 270 +15 400 -15 270 +15 450 V
Greatest Change in Drain -10V VS 10V Source ON Resistance -r r DrDS(ON) = DS(ON)MAX DS(ON)MIN Between Channels, rDS(ON)AVG. rDS(ON) Source OFF Leakage Current, IS(OFF) Drain OFF Leakage Current, ID(OFF) DG526, DG527 DG528, DG529 DG526 DG527 DG528 DG529 Drain ON DG526 Leakage Current, ID(ON) DG527 Sequence Each Switch On VAL = 0.8V and VAH = 2.4V (Note 5) VEN = 0V VEN = 0V VS = 10V, VD = +10V VS = 10V, VD = +10V VS = 10V, VD = +10V VS = 10V, VD = +10V VS = 10V, VD = +10V VS = 10V, VD = +10V VD = VS(ALL) = 10V VD = VS(ALL) = 10V
-
6
-
-
6
-
%
-1 -1 -10 -5 -10 -10 -10 -5
0.02 -0.005 0.2 0.2 -0.015 -0.008 0.2 0.2
1 1 10 5 10 10 10 5
-5 -20 -20 -
0.02 -0.005 0.2 0.2 0.015 0.008 0.2 0.2
5 20 20 -
nA nA nA nA nA nA nA nA
12-6
DG526, DG527, DG528, DG529
Electrical Specifications
(Note 3) V+ = +15V, V- = -15V, GND = 0V, WR = 0V, RS = 2.4V, EN = 2.4V, TA = 25oC, Unless Otherwise Specified (Continued) A SUFFIX PARAMETER Drain ON DG528 Leakage Current, ID(ON) DG529 (Continued) SUPPLY Positive Supply Current, I+ DG526, DG527 DG528, DG529 DG526, DG527 DG528, DG529 VEN = 0V All VA = 0V VEN = 0V All VA = 0V -2.0 -1.5 2.0 -1.2 3.0 2.5 -1.5 2.0 -1.2 -2.5 mA mA mA mA (NOTE 6) TEST CONDITIONS Sequence Each Switch On VAL = 0.8V and VAH = 2.4V (Note 5) VD = VS(ALL) = 10V VD = VS(ALL) = 10V MIN -10 -10 (NOTE 2) TYP -0.03 -0.015 MAX 10 10 B AND C SUFFIX MIN -20 -20 (NOTE 2) TYP -0.03 -0.015 MAX 20 20 UNITS nA nA
Positive Supply Current, I-
Electrical Specifications
TA = Over Operating Temperature Range, V+ = +15V, V- = -15V, GND = 0V, WR = 0V, RS = 2.4V, EN = 2.4V Unless Otherwise Specified A SUFFIX B AND C SUFFIX MAX MIN (NOTE 2) TYP MAX UNITS
PARAMETER INPUT Address Input Current Input Voltage High, IAH Address Input Current, Input Voltage Low, IAL DG526, DG527 DG528, DG529
(NOTE 6) TEST CONDITIONS
MIN
(NOTE 2) TYP
VA = 2.4V VA = 15V VA = 2.4V VA = 0V VA(ALL) = 0V, RS = 0V, WR = 0V
-30 -10 -10 -30 -30
-
30 -
-30 -30 -30
-
30 -
A A A A A A
VA = 0V
SWITCH Analog Signal Range, VANALOG Drain Source ON Resistance, rDS(ON) Source Off Leakage Current, IS(OFF) Drain OFF Leakage Current, ID(OFF) DG526 DG527 DG528 DG529 Drain ON DG526 Leakage Current, ID(ON) DG527 DG528 DG529 Sequence Each Switch On, VAL = 0.8V, VAH = 2.4V (Note 5) Note 7 VD = 10V, VAL = 0.8V, VAH = 2.4V, IS = -200A, Sequence Each Switch ON VEN = 0V VEN = 0V VS = 10V, VD = +10V VS = 10V, VD = +10V VS = +10V, VD = 10V VD = VS(ALL) = 10V -15 -50 -300 -200 -200 -100 -300 -200 -200 -100 +15 500 50 300 200 200 100 300 200 200 100 -300 -200 -200 -100 -300 -200 -200 -100 500 300 200 200 100 300 200 200 100 % nA nA nA nA nA nA nA nA nA
12-7
DG526, DG527, DG528, DG529
Minimum Input Timing Requirements
PARAMETER WRITE Pulse Width, tWW Over Full Temperature Range MEASURED TERMINAL WR, See Figure 1 MIN 300 180 30 500 UNITS ns ns ns ns
A, EN Data Valid After WRITE (Stabilization Time), tDW A0 , A1 , (A2), EN, WR; See Figure 1 A, EN Data Valid After WRITE (Hold Time), tWD RESET Pulse Width, tRS NOTES: A0 , A1 , (A2), EN, WR; See Figure 1 RS, (Note 6), VS = 5V, See Figure 2
1. Signals on VS , VD or VIN exceeding V+ or V- will be clamped by internal diodes. Limit diode forward current to maximum current ratings. 2. Typical values are for design aid only, not guaranteed and not subject to production testing. 3. The algebraic convention whereby the most negative value is a minimum, and most positive value is a maximum, is used in this datasheet. 4. OFF Isolation = 20 --------- , where VS = input to OFF switch, and VD = output due to VS . 5. ID(ON) is leakage from driver into "ON" switch. 6. Period of Reset (RS) pulse must be at least 50s during or after power ON. 7. Parameter not tested. Parameter guaranteed by design or characterization.
VS VD
Test Circuits and Waveforms
3V WR 0 tWW tWD tDW 3V A0 , A1 , (A2) EN 0 2.0V 0.8V SWITCH OUTPUT 0V VO tOFF(RS) 0.8VO 1.5V RS 0 tRS 3V 1.5V
FIGURE 1. WR TIMING WAVEFORMS
FIGURE 2. RS TIMING WAVEFORMS
+2.4V V+ EN DG528 RS
+15V
+2.4V V+ 10V EN DG529 RS
+15V
S1
S1B
10V
S2 THRU S7 A0 A1 A2 GND 50 -15V WR V1M 35pF S8 +10V
S2A THRU S4A , DA S2B , AND S3B A0 S4B +10V SWITCH OUTPUT VDB 1M -15V 35pF
LOGIC INPUT
D
SWITCH OUTPUT VD
LOGIC INPUT 50
A1 GND WR
DB V-
FIGURE 3A. tTRANSITION SWITCHING TIME TEST CIRCUIT
FIGURE 3B. tTRANSITION SWITCHING TIME TEST CIRCUIT
Similar connections for DG526
Similar connections for DG527
12-8
DG526, DG527, DG528, DG529 Test Circuits and Waveforms
(Continued)
3V 50% 0 VS1 0.8VS1 SWITCH OUTPUT VD
0
0.8VS8 VS8 TRANSITION S1 ON LOGIC INPUT tr < 20ns tf < 20ns S8 ON TRANSITION
FIGURE 3C. tTRANSITION SWITCHING TIME WAVEFORM
+2.4V 3V 50% 0 RS SWITCH OUTPUT VD VS 80% LOGIC INPUT tOPEN 50 LOGIC INPUT tr < 20ns tf < 20ns A0 , A1 , (A2) GND WR EN DG528 DG529 V+
+15V
ALL S AND DA
+5V
0V
DB (D) V1k -15V
SWITCH OUTPUT VD 35pF
FIGURE 4A. tOPEN (BREAK-BEFORE-MAKE) SWITCHING TIME WAVEFORM
FIGURE 4B. tOPEN (BREAK-BEFORE-MAKE) SWITCHING TIME TEST CIRCUIT Similar connections for DG526, DG527
+2.4V RS EN DG528 V+
+15V RS -5V EN
+2.4V V+
+15V
S1
S1B DG529 S1A THRU S4A, DA , S2B , S3B , S4B
-5V
S2 THRU S7 A0 A1 A2 EN 50 GND WR V1k -15V 35pF D SWITCH OUTPUT VD EN 50 A0 A1 GND
DB WR V1k -15V
SWITCH OUTPUT VDB 35pF
FIGURE 5A. ENABLE tON AND tOFF SWITCHING TIME TEST CIRCUIT Similar connections for DG526
FIGURE 5B. ENABLE tON AND tOFF SWITCHING TIME TEST CIRCUIT Similar connections for DG527
12-9
DG526, DG527, DG528, DG529 Test Circuits and Waveforms
(Continued)
3V 50% 0 tON (EN) SWITCH OUTPUT 0 VD 0.1VO tOFF (EN)
0.9VO VO VS
EN tr < 20ns tf < 20ns
FIGURE 5C. ENABLE tON AND tOFF SWITCHING TIME WAVEFORMS
+2.4V tr < 20ns tf < 20ns 3V 1.5V 0V SWITCH OUTPUT VO 50% EN DG528 DG529 A0 , A1 , (A2) V+
+15V
S1 OR S1B
+5V
tON (WR) RS 0.2VO RS WR LOGIC INPUT WR GND
REMAINING SWITCHES
0V
DB (D) V1k -15V
SWITCH OUTPUT VO 35pF
Device must be reset prior to applying WR pulse.
FIGURE 6A. WRITE tON SWITCHING TIME WAVEFORMS
Similar connections for DG526, DG527
FIGURE 6B. WRITE tON SWITCHING TIME TEST CIRCUIT
+2.4V
+15V V+ S1 OR S1B
tr < 20ns tf < 20ns 3V RS 1.5V 0V 50%
EN
DG528 DG529
+5V
A0 , A1 , (A2) REMAINING SWITCHES
tOFF (RS) RS SWITCH OUTPUT VO 0.8VO GND RS -15V WR DB (D) V1k 35pF SWITCH OUTPUT VO
FIGURE 7A. RESET tOFF SWITCHING TIME WAVEFORMS
FIGURE 7B. RESET tOFF SWITCHING TIME TEST CIRCUIT
Similar connections for DG526, DG527
12-10
DG526, DG527, DG528, DG529 Test Circuits and Waveforms
(Continued)
+15V V+ A0 , A1 , (A2) 3V EN 0 Sx DG528 DG529 D VO RS +2.4V
VO
VO CL = 1000pF
GND EN
WR
V-
VO is the measured voltage error due to charge injection. The error voltage in Coulombs is Q = CL x VO . FIGURE 8A. CHARGE INJECTION WAVEFORMS
-15V
FIGURE 8B. CHARGE INJECTION TEST CIRCUIT
Similar connections for DG526, DG527
Typical Performance Curves
550 500 450 (C) 400 rDS (ON) () 350 300 250 200 150 100 50 0 -15 -13 -11 -9 -7 -5 (A) (B) (C) (D) V+ = +15V, V- = -15V V+ = +12V, V- = -12V V+ = +10V, V- = -10V V+ = +7.5V, V- = -7.5V rDS(ON) () (B) (A) IO = -200A VEN = +5V (D) 360 320 280 +10V SIGNALS 240 200 160 120 80 40 0 -55 -25 0 25 45 70 100 125 400 V+ = +15V V- = -15V VEN = 2.4V IO = -200A +10V SIGNALS
-3 -1 0 +1 +3 +5 +7 +9 +11 +13 +15
ANALOG SIGNAL VOLTAGE (V)
TEMPERATURE (oC)
FIGURE 9. rDS(ON) vs ANALOG SIGNAL VOLTAGE vs SUPPLY VOLTAGE
FIGURE 10. TYPICAL rDS(ON) VARIATION WITH TEMPERATURE
12-11
DG526, DG527, DG528, DG529 Truth Tables
DG526 A3 Latching X A2 X A1 X A0 X EN X WR RS 1 ON SWITCH Maintains Previous Switch State None (Latches Cleared) None 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Latching A2 X A1 X DG527 A0 X EN X WR RS 1 ON SWITCH Maintains Previous Switch State None (Latches Cleared) None 1 2 3 4 5 6 7 8
Reset
X
X
X
X
X
X
0
Reset
X
X
X
X
X
0
Transparent Operation
X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Transparent Operation
X 0 0 0 0 1 1 1 1
X 0 0 1 1 0 0 1 1
X 0 1 0 1 0 1 0 1
0 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1
Logic "1" = VAH , VENH 2.4V
Logic "0" = VAL , VENL 0.8V
DG528 A2 X X X 0 0 0 0 1 1 1 1 A1 X X X 0 0 1 1 0 0 1 1 A0 X X X 0 1 0 1 0 1 0 1 EN X X 0 1 1 1 1 1 1 1 1 X 0 0 0 0 0 0 0 0 0 WR RS 1 0 1 1 1 1 1 1 1 1 1 ON SWITCH Maintains Previous Switch Condition None (Latches Cleared) None 1 2 3 4 5 6 7 8 A1 X X X 0 0 1 1 A0 X X X 0 1 0 1 EN X X 0 1 1 1 1 X 0 0 0 0 0 WR
DG529 RS 1 0 1 1 1 1 1 ON SWITCH Maintains Previous Switch Condition None (Latches Cleared) None 1 2 3 4
Logic "1": VAH 2.4V Logic "0": VAL 0.8V
12-12
DG526, DG527, DG528, DG529 Die Characteristics
DIE DIMENSIONS: 3810m x 2769m METALLIZATION: Type: Al Thickness: 10kA 1kA PASSIVATION: Type: PSG Over Nitride PSG Thickness: 7kA 1.4kA Nitride Thickness: 8kA 1.2kA WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm2
Metallization Mask Layout
DG526
PIN 11 S9 PIN 12 GND PIN 13 WR PIN 10 S10 PIN 9 S11 PIN 8 S12 PIN 7 S13 PIN 6 S14 PIN 5 S15 PIN 4 S16 PIN 3 RS
PIN 14 A3 PIN 15 A2
PIN 2 NC
PIN 16 A1 PIN 17 A0
PIN 1 V+ PIN 28 D
PIN18 EN
PIN 27 V-
PIN 19 S1
PIN 20 PIN 21 S2 S3
PIN 22 PIN 23 S4 S5
PIN 24 S6
PIN 25 S7
PIN 26 S8
12-13
DG526, DG527, DG528, DG529 Die Characteristics
DIE DIMENSIONS: 3810m x 2769m METALLIZATION: Type: Al Thickness: 10kA 1kA PASSIVATION: Type: PSG Over Nitride PSG Thickness: 7kA 1.4kA Nitride Thickness: 8kA 1.2kA WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm2
Metallization Mask Layout
DG527
PIN 11 S1B PIN 12 GND PIN 13 WR PIN 10 S2B PIN 9 S3B PIN 8 S4B PIN 7 S5B PIN 6 S6B PIN 5 S7B PIN 4 S8B PIN 3 RS
PIN 14 NC PIN 15 A2
PIN 2 DB
PIN 16 A1 PIN 17 A0
PIN 1 V+ PIN 28 DA
PIN18 EN
PIN 27 V-
PIN 19 S1A
PIN 20 PIN 21 S2A S3A
PIN 22 PIN 23 S4A S5A
PIN 24 S6A
PIN 25 S7A
PIN 26 S8A
12-14
DG526, DG527, DG528, DG529 Die Characteristics
DIE DIMENSIONS: 3100m x 2083m METALLIZATION: Type: Al Thickness: 10kA 1kA PASSIVATION: Type: PSG Over Nitride PSG Thickness: 7kA 1.4kA Nitride Thickness: 8kA 1.2kA WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm2
Metallization Mask Layout
DG528
PIN 15 GND
PIN 14 V+
PIN 13 S5
PIN 12 S6
PIN 11 S7
PIN 16 A2
PIN 17 A1
PIN 18 RS
PIN 10 S8
PIN 1 WR
PIN 9 D
PIN 2 A0
PIN 8 S4
PIN 3 EN
PIN 4 V-
PIN 5 S1
PIN 6 S2
PIN 7 S3
12-15
DG526, DG527, DG528, DG529 Die Characteristics
DIE DIMENSIONS: 3100m x 2083m METALLIZATION: Type: Al Thickness: 10kA 1kA PASSIVATION: Type: PSG Over Nitride PSG Thickness: 7kA 1.4kA Nitride Thickness: 8kA 1.2kA WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm2
Metallization Mask Layout
DG529
PIN 15 V+
PIN 14 S1G
PIN 13 S2B
PIN 12 S3B
PIN 11 S4B
PIN 16 GND
PIN 17 A1
PIN 18 RS
PIN 10 S8A
PIN 1 WR
PIN 9 DA
PIN 2 A0
PIN 8 S4A
PIN 3 EN
PIN 4 V-
PIN 5 S1A
PIN 6 S2A
PIN 7 S3A
12-16

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